This invention relates to dielectric isolation for integrated semiconductor devices, and more particularly to a method of manufacturing integrated semiconductor circuit devices, which is adapted to simultaneously form narrow isolation regions and wide field regions, with high surface planarity, by means of simple steps.
In bipolar type integrated semiconductor circuit devices, the active elements are generally isolated by the PN junction isolation. However, with increasing demand for smaller device sizes and higher packing density, it has become necessary to reduce the isolation areas. The PN junction isolation has been gradually superseded by the oxide isolation (the so-called Isoplanar Process) using thick oxide formed in the silicon substrate through local oxidation.
The oxide isolation method typically comprises placing on a silicon substrate an oxidation-resistant masking layer formed of a composite layer of a thin silicon oxide film and a silicon nitride film, etching the surface of the silicon substrate to form mesa regions for active elements under the masking layers, and thermally oxidizing the silicon substrate to form thick silicon oxide as field isolation regions surrounding the mesa regions. According to this method, the thermally grown thick oxide has increased volume to present surfaces nearly flush with the surfaces of the device regions.
As compared with the PN junction, the oxide isolation can reduce the widths and areas of the isolation regions, and can also reduce stray capacitances between the surface conductors and the substrate due to the thick silicon oxide forming all regions other than the device regions (hereinafter called "the field region(s)"), thereby contributing to increase of the switching speed of the resulting transistors.
However, during the above thermal oxidation step, since lateral oxidation causes formation of "bird's beak" and "bird's head" between the silicon substrate and the oxidation-resistance masking layer, the widths of the isolation regions become greater than an allowable minimum dimension obtained by the conventional photolithography, which is approximately 10 microns. Also, the bird's beak and bird's head spoils the perfect planarity of the substrate surface.
To overcome such disadvantages, an improved isolation technique has been proposed as represented, e.g. by a process described in a paper entitled "A Method for Area Saving Planar Isolation Oxidation Protected Sidewalls" by D. Kahng et al, published in Solid-State Science And Technology issued by J. Electrochemistry Society, Vol. 127, No. 11, November, 1980, pp. 2468-2470. According to this process (hereinafter referred to as "Improved Local Oxidation Process"), in addition to a first oxidation-resistant layer of silicon nitride deposited over the top surfaces of mesa regions, a second oxidation-resistant layer of silicon nitride is deposited, by chemical vapor deposition, on the sidewalls of the mesa regions. The improved Local Oxidation Process can thus prevent widening of the isolation regions caused by the lateral oxidation, and formation of bird's beak and bird's head and can achieve flattening of the silicon substrate surface irrespective of the width of the isolation regions to be formed, by simple steps.
However, according to this process, it takes an impracticably very long time to form thick field regions by oxidizing through an epitaxial layer on the surface of the silicon substrate. To shorten the oxidizing time, buried regions have to be formed in the surface of a silicon substrate by using a mask before the formation of an epitaxial layer on the entire surface of the silicon substrate, and then mesa regions are formed by selectively etching the epitaxial layer with a second mask. Therefore, more critical mask aligning tolerances are required in aligning the second mask with the formerly formed buried region. Furthermore, in the case of narrow isolation regions, a P.sup.+ channel stop layer formed under the bottom of the isolation region can spread to the nearby N buried region, resulting in increased parasitic capacitance, increased leak current between the base region and the P.sup.+ channel stop layer and reduced breakdown voltage.
Recently, a trench isolation technique has been developed, which utilizes a reactive ion etching (RIE) process capable of etching a silicon substrate vertically to the substrate surface to form grooves of a given width having vertical sidewalls. The trench isolation technique is represented, e.g. by a process described in a paper entitled "U-Groove Isolation Technique For High Speed Bipolar VLS's" by Akio Hayasaka et al, published in IEDM 82, 1982, pp. 62-65. According to this process, a silicon substrate is etched using RIE to form deep, shear U-grooves. The grooves or trenches are oxidized to form a dielectric material such as silicon dioxide along their walls, and covered with a dielectric film such as silicon nitride. A polycrystalline semiconductor material is then deposited over the silicon substrate so as to bury the grooves, and then etched back to form a flat surface on the silicon substrate. This process will hereinafter be referred to as "Trench Isolation Process".
In fabricating bipolar integrated circuit devices by means of the Trench Isolation Process, deep isolation grooves can be formed in the silicon substrate so as to penetrate a buried layer formed by diffusion throughout the whole area of the silicon substrate, thereby dispensing with the use of a mask for formation of such buried layer, which has conventionally been employed. However, according to the Trench Isolation Process, it is difficult to simultaneously form a flat surface over small width isolation regions and large width field regions. That is, a separate flattening step using a mask is required to obtain required surface planarity, which leads to an increased number of fabricating steps, and also requires a special mask aligning step because of the tight mask aligning tolerances.
In fabricating bipolar integrated circuit devices, it is desirable to divide a portion of the transistor-forming region in the vicinity of the substrate surface into base and collector contact regions so as to have the buried layer in common with each other, that is, to have the buried layer underlaying both the two regions, in order to assure a high switching speed of the transistor. To this end, it is necessary to form deep trenches for separating device areas of integrated transistor devices and shallow trenches for separating base and collector contact regions in an array satisfying the above dividing requirements, and two masks have to be provided for forming respective deep and shallow trenches. These requirements cause complication of the fabricating steps.